1. Field of the Invention
The present invention relates generally to methods for forming vias through dielectric layers within microelectronic fabrications. More particularly, the present invention relates to methods for forming with attenuated contact resistance incompletely landed vias through dielectric layers to access patterned conductor layers within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and patterned microelectronic conductor layer dimensions have decreased, it has become more common in the art of microelectronic fabrication to form interposed between the patterns of narrow linewidth patterned microelectronic conductor layers within microelectronic fabrications low dielectric constant microelectronic dielectric materials. Within the context of the present invention, narrow linewidth patterned microelectronic conductor layers within microelectronic fabrications are typically characterized by a linewidth of less than about 0.5 microns, more typically of a linewidth of from about 0.1 to about 0.4 microns. Similarly, low dielectric constant microelectronic dielectric materials when employed within microelectronic fabrications formed interposed between the patterns of patterned microelectronic conductor layers within microelectronic fabrications are typically characterized by a dielectric constant of less than about 4.0, more typically of a dielectric constant of from about 1.5 to about 3.8. In comparison, conventional silicon containing dielectric materials, such as but not limited to silicon oxide dielectric materials, silicon nitride dielectric materials and silicon oxynitride dielectric materials, typically have a dielectric constant in a range of from about 4 to about 8 .
Within the context of the present disclosure, low dielectric constant microelectronic dielectric materials may include, but are not limited to: (1) spin-on-glass (SOG) low dielectric constant dielectric materials (such as but not limited to silicate spin-on-glass (SOG) dielectric materials and silsesquioxane spin-on-glass (SOG) dielectric materials (such as but not limited to hydrogen silsesquioxane spin-on-glass (SOG) dielectric materials, carbon bonded hydrocarbon silsesquioxane spin-on-glass (SOG) dielectric materials and carbon bonded fluorocarbon silsesquioxane spin-on-glass (SOG) dielectric materials)); (2) spin-on-polymer (SOP) low dielectric constant dielectric materials (such as but not limited to polyimide spin-on-polymer (SOP) dielectric materials, poly arylene ether spin-on-polymer (SOP) dielectric materials and fluorinated analogs thereof; (3) amorphous carbon dielectric materials (including fluorinated analogs thereof); and (4) fluorinated conventional silicon containing dielectric materials (such as but not limited to fluorosilicate glass (FSG) dielectric materials).
Low dielectric constant dielectric materials are desirable when formed interposed between the patterns of narrow linewidth patterned microelectronic conductor layers within microelectronic fabrications since such low dielectric constant dielectric materials provide microelectronic fabrications with enhanced microelectronic fabrication speed, reduced patterned microelectronic conductor layer parasitic capacitance and reduced patterned microelectronic conductor layer cross-talk.
While microelectronic fabrications having formed therein narrow linewidth patterned microelectronic conductor layers having formed interposed between their patterns low dielectric constant microelectronic dielectric materials are thus desirable within the art of microelectronic fabrication, microelectronic fabrications having formed therein narrow linewidth patterned microelectronic conductor layers having formed interposed between their patterns low dielectric constant microelectronic dielectric materials are nonetheless not formed entirely without problems in the art of microelectronic fabrication.
In particular, it is known in the art of microelectronic fabrication that when forming a conductor stud layer into a via formed through a dielectric layer formed of a low dielectric constant microelectronic dielectric material to access a narrow linewidth patterned microelectronic conductor layer within a microelectronic fabrication there is often experienced contact resistance increases since many low dielectric constant microelectronic dielectric materials readily sorb and desorb moisture and solvents which may contribute to oxidation or corrosion of the conductor stud layer and/or the narrow linewidth patterned microelectronic conductor layer. Similarly, such sorbtion and desorbtion induced contact resistance increases are often exacerbated under circumstances where the via formed through the microelectronic dielectric layer to access the narrow linewidth patterned microelectronic conductor layer is not completely landed, but rather partially offset, from the narrow linewidth patterned microelectronic conductor layer, since under such circumstances there is typically not formed a contiguous and reliable interface between the narrow linewidth patterned microelectronic conductor layer and the conductor stud layer.
It is thus towards the goal of forming within the art of microelectronic fabrication, with attenuated contact resistance, conductor stud layers into vias through dielectric layers to access patterned conductor stud layers within the microelectronic fabrications, where the vias are incompletely landed upon patterned conductor layers within those microelectronic fabrications, that the present invention is directed. More particularly, the present invention is directed towards the foregoing object under circumstances where the dielectric layers are formed of low dielectric constant dielectric materials.
Various methods have been disclosed in the art of microelectronic fabrication for forming microelectronic conductor structures and/or microelectronic dielectric structures with desirable properties within microelectronic fabrications.
For example, Wu et al., in U.S. Pat. No. 5,432,073, discloses a method for forming within a microelectronic fabrication a conductor stud layer into a via formed through a dielectric layer formed at least in part of a spin-on-glass (SOG) dielectric material to access a patterned conductor layer within the microelectronic fabrication, while avoiding a contact resistance increase of the conductor stud layer with respect to the patterned conductor layer. The method realizes the foregoing object by degassing the spin-on-glass (SOG) dielectric material exposed within the via at a temperature of from about 300 to about 500 degrees centigrade prior to forming within the via the conductor stud layer.
In addition, Kishimoto et al., in U.S. Pat. No. 5,506,177, discloses a method for forming within a microelectronic fabrication a spin-on-glass (SOG) sandwich composite planarizing dielectric layer construction with enhanced crack resistance and enhanced moisture resistance, while employing a hydrogen silsesquioxane (HSQ) spin-on-glass (SOG) low dielectric constant dielectric material when forming a spin-on-glass (SOG) planarizing layer within the spin-on-glass (SOG) sandwich composite planarizing dielectric layer construction. The method realizes the foregoing object by employing a two step thermal annealing method for curing and thermal annealing of the spin-on-glass (SOG) planarizing layer, wherein a second thermal annealing step within the two step thermal annealing method reflows a thermally cured hydrogen silsesquioxane spin-on-glass (SOG) dielectric material formed within a first thermal annealing step within the two step thermal annealing method.
Further, Havemann, in U.S. Pat. No. 5,565,384, discloses a method for forming, with enhanced microelectronic fabrication stability, reliability and performance, a via through a dielectric layer to access a patterned conductor layer within a microelectronic fabrication. The method employs a low dielectric constant dielectric material interposed between the patterns of a patterned microelectronic conductor layer within the microelectronic fabrication, where the low dielectric constant dielectric material serves as an etch stop material when forming the via through an upper lying dielectric layer formed thereupon to access the patterned conductor layer within the microelectronic fabrication.
Still further, Ahlburn et al., in U.S. Pat. No. 5,607,773, disclose a method for forming within a microelectronic fabrication a low dielectric constant spin-on-glass (SOG) sandwich composite planarizing dielectric layer construction with avoiding a need for a plasma etchback processing step for etching back a low dielectric constant spin-on-glass (SOG) planarizing layer within the low dielectric constant spin-on-glass (SOG) sandwich composite planarizing dielectric layer construction. The method realizes the foregoing object by employing when forming the low dielectric constant spin-on-glass (SOG) planarizing layer a hydrogen silsesquioxane (HSQ) spin-on-glass (SOG) planarizing dielectric material which is pyrolized to form a low density and low dielectric constant silicon oxide dielectric material for which reactive ion etch (RIE) etchback processing is not needed when forming the low dielectric constant spin-on-glass (SOG) sandwich composite planarizing dielectric layer construction.
Still further, Chang, in U.S. Pat. No. 5,643,407, discloses a method for forming within a microelectronic fabrication a via through a spin-on-glass (SOG) sandwich composite planarizing dielectric layer construction to access a patterned conductor layer formed beneath the spin-on-glass (SOG) sandwich composite planarizing dielectric layer construction, where when a conductor stud layer is formed into the via there is an attenuated contact resistance of the conductor stud layer with respect to the patterned conductor layer. The method realizes the foregoing object by first treating portions of a spin-on-glass (SOG) planarizing dielectric layer exposed within the via with a nitrogen plasma prior to forming within the via the conductor stud layer.
Still further, Inoue et al., in U.S. Pat. No. 5,750,403, discloses a method for forming within a microelectronic fabrication a thermally cured hydrogen silsesquioxane (HSQ) dielectric layer absent thermally induced projections from the thermally cured hydrogen silsesquioxane (HSQ) dielectric layer. The method realizes the foregoing object by first thermally curing a hydrogen silsesquioxane (HSQ) dielectric layer within a nitrogen atmosphere to form a once thermally cured hydrogen silsesquioxane (HSQ) dielectric layer of a pre-ceramic phase, and then after forming a barrier dielectric layer upon the once thermally cured hydrogen silsesquioxane (HSQ) dielectric layer thermally curing again the once thermally cured hydrogen silsesquioxane (HSQ) dielectric layer in a second thermal annealing method to form from the once thermally cured hydrogen silsesquioxane (HSQ) dielectric layer of the pre-ceramic phase a twice thermally cured hydrogen silsesquioxane (HSQ) dielectric layer of the ceramic phase.
Still further, Guo et al., in U.S. Pat. No. 5,763,010 discloses a method for forming within a microelectronic fabrication a halogen doped silicon oxide dielectric layer with enhanced stability of the halogen doped silicon oxide dielectric layer with respect to outgassing of halogen atoms from the halogen doped silicon oxide dielectric layer. The halogen doped silicon oxide dielectric layer realizes the foregoing object by thermally outgassing from the halogen doped silicon oxide dielectric layer mobile halogen atoms at a temperature of from about 300 to about 500 degrees centigrade prior to forming upon the thermally outgassed halogen doped silicon oxide dielectric layer a barrier layer.
Finally, Jeng et al., in U.S. Pat. No. 5,818,111, disclose a method for forming within a microelectronic fabrication a dielectric layer comprising a hydrogen silsesquioxane (HSQ) dielectric material formed with enhanced properties within the microelectronic fabrication. The method employs forming interposed between sub-layers of the hydrogen silsesquioxane (HSQ) dielectric material within the dielectric layer intervening stabilizing sub-layers of a silicon oxide dielectric material.
Desirable in the art of microelectronic fabrication are additional methods and materials for forming within microelectronic fabrications, with attenuated contact resistance, conductor stud layers into vias through dielectric layers to access patterned conductor layers within the microelectronic fabrications, where the vias are incompletely landed upon patterned conductor layers within those microelectronic fabrications. More particularly desirable in the art of microelectronic fabrication are methods and materials directed towards the foregoing object, where the dielectric layers are formed of low dielectric constant dielectric materials.
It is towards the foregoing objects that the present invention is both generally and more specifically directed.
A first object of the present invention is to provide a method for forming within a microelectronic fabrication a via through a dielectric layer to access a patterned conductor layer formed beneath the dielectric layer, where the via is incompletely landed upon the patterned conductor layer.
A second object of the present invention is to provide a method in accord with the first object of the present invention, where when a conductor stud layer is formed into the via, the conductor stud layer is formed with attenuated contact resistance with respect to the patterned conductor layer.
A third object of the present invention is to provide a method in accord with the first object of the present invention and the second object of the present invention, wherein the dielectric layer is formed of a low dielectric constant dielectric material.
A fourth object of the present invention is to provide a method in accord with the first object of the present invention, the second object of the present invention and the third object of the present invention, which method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a method for forming a via through a dielectric layer. To practice the method of the present invention, there is first provided a substrate. There is then formed over the substrate a patterned conductor layer. There is then formed covering the patterned conductor layer a dielectric layer. There is then formed through the dielectric layer a via to access the patterned conductor layer, where the via is incompletely landed upon the patterned conductor layer. There is then purged the via while employing a vacuum purging method to form a purged via. There is then passivated the purged via and passivated the patterned conductor layer while employing a plasma passivation method to form a plasma passivated purged via and a plasma passivated patterned conductor layer. Finally, there is then formed into the plasma passivated purged via a conductor stud layer.
There is provided by the present invention a method for forming within a microelectronic fabrication a via through a dielectric layer to access a patterned conductor layer, where the via is incompletely landed with respect to the patterned conductor layer, and where when a conductor stud layer is formed into the via, the conductor stud layer is formed with attenuated contact resistance. The present invention realizes the foregoing objects by employing after forming a via through a dielectric layer, which via is incompletely landed with respect to a patterned conductor layer formed beneath the dielectric layer within the microelectronic fabrication: (1) a purging of the via to form a purged via, followed by; (2) a passivating of the purged via and the patterned conductor layer to form a plasma passivated purged via and a plasma passivated patterned conductor layer prior to forming into the plasma passivated purged via a conductor stud layer contacting the plasma passivated patterned conductor layer.
While it is not entirely clear within the present invention why a conductor stud layer when formed into a plasma passivated purged via accessing a plasma passivated patterned conductor layer is formed with an attenuated contact resistance with respect to the plasma passivated patterned conductor layer in comparison with an otherwise equivalent conductor stud layer formed into a non-purged via and/or non-plasma passivated via to contact a non-plasma passivated patterned conductor layer, it is nonetheless clear that a conductor stud layer formed into a plasma passivated purged via is formed within the context of the present invention with an attenuated contact resistance with respect to a plasma passivated patterned conductor layer accessed by the plasma passivated purged via.
The method of the present invention is readily commercially implemented. The present invention employs methods and materials which are generally known in the art of microelectronic fabrication. Since it is a process control and materials selection which provides at least in part the present invention, rather than the existence of methods and materials which provides the present invention, the method of the present invention is readily commercially implemented.